1. Field of the Invention
This invention relates to correction of the swapping of fields in a field memory type synchronizer.
2. Background of the Invention
In many video systems, video information is sequentially transmitted in two fields. For the purposes of this specification, the respective fields will be designated as odd-numbered (ODD or O) fields and even-numbered (EVEN or E) fields. Each field contains a large number of horizontal lines of data which are sequentially scanned across and then down a screen. When an ODD field has been completed, an EVEN field is processed similarly. However the horizontal scan lines, for the EVEN fields are displayed vertically offset between the horizontal scan lines in a process called interlacing.
Because of cost, it is preferable to employ a 1-field memory which is small in capacity, as a synchronizer for the synchronous conversion of video signals. In the 1-field memory system, owing to the phase relation between the input video signal and the reference synchronization of the synchronizer, the odd-numbered (ODD or O) field may be read as an even-numbered (EVEN or E) field, or vice versa. That is, the timing of the reading of the field memory is offset in time from its writing to the extent that the reading of a location in the field memory for one type of field occurs when that location actually contains the other type field.
In this case, the odd-numbered fields and the even-numbered fields are inverted in vertical position. This can be corrected with only a slight offset in screen image by time delaying by one horizontal scanning line period (hereinafter referred to as "1H") the fields which have become the odd-numbered fields by the swapping of fields. This will become more apparent from FIG. 1. Part (a) of FIG. 1 shows the correctly oriented lines formed by input signals, part (b) shows the case where the fields are simply swapped with each other, and the part (c) the case where, after swapping, the odd-numbered fields are delayed by 1H.
A conventional field memory synchronizer of this type is as shown in FIG. 2. The operation of the field memory synchronizer will be described with reference to FIG. 2.
In FIG. 2, a video signal applied to a video signal input terminal 1 is converted into a digital signal by an A/D (analog-to-digital) converter 2 with the aid of a clock pulse generated by a writing clock pulse generating section 3. The digital signal is written in a field memory 6. On the other hand, with the aid of the writing clock pulse, a writing address generating section 4 outputs a writing address signal, which is applied through a memory control section 5 to the field memory 6 to control the field memory 6.
On the read-out side, a reading clock pulse generating section 8 produces a reading clock pulse with the aid of a reference signal applied to a reference signal input terminal 7. The clock pulse is applied to a D/A (digital-to-analog) converter 13 and a reading address generating section 9 so that the reading address generating section 9 produces a reading address signal. Similarly as in the case of the writing address signal, the reading address signal is applied through the memory control section 5 to the field memory 6 so that an address from which data is to be read out of the field memory 6 is specified.
A field swap detecting section 10 receives signals based on the writing address and the reading address and outputs a signal to trip the armature of a switch 12 over to its contact b when, during field swapping, the odd-numbered fields are read. As a result, the odd-numbered field area is read after the swapping of the fields, and the digital signal read out of the memory 6 is applied to a 1H delay line 11 so that the swapped fields are rearranged. The output signal of the 1H delay line 11 is applied to the D/A converter 13, so that it is provided, as an analog signal, at the output terminal 14.
The conventional field memory synchronizer is designed as described above and therefore needs the 1H delay line 11 and the switch 12. In order to perform the 1H delay in a digital mode as shown in FIG. 2, the 1H delay line 11 may be made up of shift registers. However, in this case, a number of shift registers must be used because one clock pulse period is much shorter than one horizontal synchronizing period. If the number of bits quantized is represented by n, then n switch circuits are required because the switch 12 must be provided for each of the bits. Thus, the conventional field memory synchronizer is disadvantageous in that the number of circuits is relatively large and accordingly the manufacturing cost is also relatively high.